top of page

​Algorithm: Optimum Scheduling Under Resource & Timing Constraints Using ASAP and ALAP Scheduling Algorithm (LP solver).

EXPERIENCE

The National Engineering
Conference 
07.17.2018
IEEE
Seminar
03.21.2018

UPCOMING EVENTS

Computer Architecture Symposium 2020
04.15.2020 

Finding a given circuits path is sensitizable or non sensitizable.

Using Cadence virtuoso schematic & layout design of different multistage circuits to find out optimal stage by calculating transition delay (checking LVS, DRC, QRC & Parasitic Extraction).

Equivalence and Containment Check for C17, C880, C1355, C1908, C3540 also finding max node in manager before and after applying different Reordering Techniques.

ROM Memory Design Using Verilog.

bottom of page