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Cadence virtuoso schematic & layout design of different multistage circuits.

  • Writer: A.K.Biswas
    A.K.Biswas
  • Oct 19, 2017
  • 1 min read

For this task lets design first a multistage inverter schematic using Cadence virtuoso as shown in figure below.


Now you can use Launch ADE L to view the input vs output wave and can find the delay.

Use this techniques for each stage, say you have only 2 stage (2 inverter), now do the same for 3 stage and respectively. Measure the rising transition and falling transition delay for each stage.

Eventually you will be able to find the optimal stage for this circuit.

 
 
 

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